IRIS
LANUZZA, Marco
 Distribuzione geografica
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Continente #
NA - Nord America 3.399
EU - Europa 2.135
AS - Asia 377
AF - Africa 167
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 5
SA - Sud America 5
Totale 6.099
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Nazione #
US - Stati Uniti d'America 3.303
UA - Ucraina 806
DE - Germania 528
IT - Italia 324
SE - Svezia 227
SN - Senegal 163
CN - Cina 156
CA - Canada 95
TR - Turchia 89
FI - Finlandia 72
HK - Hong Kong 52
AT - Austria 51
GB - Regno Unito 35
BE - Belgio 33
FR - Francia 21
SG - Singapore 21
IN - India 16
IQ - Iraq 13
AU - Australia 11
CZ - Repubblica Ceca 9
IL - Israele 7
KR - Corea 7
JP - Giappone 6
NL - Olanda 6
EU - Europa 5
BR - Brasile 4
IE - Irlanda 4
PL - Polonia 4
GR - Grecia 2
RO - Romania 2
RU - Federazione Russa 2
ZA - Sudafrica 2
AE - Emirati Arabi Uniti 1
AM - Armenia 1
CH - Svizzera 1
EG - Egitto 1
ES - Italia 1
HR - Croazia 1
HU - Ungheria 1
ID - Indonesia 1
KW - Kuwait 1
LU - Lussemburgo 1
LV - Lettonia 1
MK - Macedonia 1
MO - Macao, regione amministrativa speciale della Cina 1
MX - Messico 1
NO - Norvegia 1
PE - Perù 1
PH - Filippine 1
PK - Pakistan 1
SK - Slovacchia (Repubblica Slovacca) 1
SL - Sierra Leone 1
TH - Thailandia 1
TW - Taiwan 1
VN - Vietnam 1
Totale 6.099
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Città #
Chandler 605
Jacksonville 443
San Mateo 303
Dearborn 250
Dakar 163
Lawrence 129
Rende 128
Roxbury 127
Bremen 114
Des Moines 87
Izmir 83
New York 83
Ottawa 80
Shanghai 74
Helsinki 72
Ashburn 65
Cambridge 59
Ann Arbor 57
Inglewood 55
Ogden 52
Vienna 46
Brooklyn 45
Wilmington 41
Beijing 35
Chicago 31
Bari 30
Brussels 30
West Jordan 30
Boardman 23
Milan 22
London 19
Cosenza 16
Munich 14
San Francisco 14
Grafing 13
Redwood City 12
Central 11
Falls Church 11
Houston 11
Singapore 11
Toronto 11
Cedar Knolls 10
Bologna 8
Hong Kong 8
Norwalk 8
Brno 7
Los Angeles 7
Nanjing 7
Ningbo 7
Rome 7
Amsterdam 6
Frankfurt am Main 6
Palermo 6
Seattle 6
Seoul 6
Vibo Valentia 6
Kilburn 5
Paris 5
Spadola 5
Sydney 5
Dublin 4
Florence 4
Mascalucia 4
Melbourne 4
Monmouth Junction 4
Turin 4
Washington 4
Changsha 3
Giv‘atayim 3
Gunzenhausen 3
Haikou 3
Heusden-Zolder 3
Markham 3
Osaka 3
Princeton 3
Redmond 3
Serra 3
Tokyo 3
Warsaw 3
Woodbridge 3
Xi'an 3
Arcueil 2
Augusta 2
Berlin 2
Bomporto 2
Brunoy 2
Canberra 2
Catania 2
Celico 2
Corsico 2
Crotone 2
Falkenstein 2
Gauteng 2
Gravina di Catania 2
Guangzhou 2
Hefei 2
Jinan 2
Kunming 2
Melendugno 2
Messina 2
Totale 3.738
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Nome #
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 126
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 125
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 103
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 99
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC 96
An Ultralow-Voltage Energy-Efficient Level Shifter 87
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 79
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 78
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 75
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 73
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 70
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 70
A high-performance fully reconfigurable FPGA-based 2D convolution processor 70
A comparative study of MWT architectures by means of numerical simulations 67
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs 66
Comparative analysis of yield optimized pulsed flip-flops 64
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits 64
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits 63
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions 63
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 63
Design of a sub-1-V nanopower CMOS current reference 63
Low-power split-path data-driven dynamic logic 62
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmentic circuits 61
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 61
A 180 nm Low-Cost Operational Amplifier for IoT Applications 60
Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations 59
A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters 59
A portable class of 3-transistor current references with low-power sub-0.5 V operation 59
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits 58
Low energy/delay overhead level shifter for wide-range voltage conversion 58
A novel ICA-based hardware system for reconfigurable and portable BCI 58
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 58
Variable precision arithmetic circuits for FPGA-based multimedia processors 56
Low-Power Level Shifter for Multi-Supply Voltage Designs 56
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 54
Design of a 3T current reference for low-voltage, low-power operation 54
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits 54
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 54
Evaluation of Dual Mode Logic in 28nm FD-SOI technology 54
Design and evaluation of high-speed energy-aware carry skip adders 53
Opto-electrical modelling and optimization study of a novel IBC c-Si solar cell 53
Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework 53
Skyrmion based microwave detectors and harvesting 52
Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells 52
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 52
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework 52
Impact of the Emitter Contact Pattern in c-Si BC-BJ Solar Cells by Numerical Simulations 52
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines 51
Designing Dynamic Carry Skip Adders: Analysis and Comparison 51
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 51
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI 50
Optimization of Rear Point Contact Geometry by Means of 3-D Numerical Simulation 50
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 50
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 49
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 49
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 49
A new low-power high-speed single-clock-cycle binary comparator 49
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing 49
A variation-aware simulation framework for hybrid CMOS/spintronic circuits 49
Low bit rate image compression core for onboard space applications 49
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 48
A new reconfigurable coarse-grain architecture for multimedia applications 48
Spin-orbit torque based physical unclonable function 48
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs 47
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 47
Double-precision Dual Mode Logic carry-save multiplier 46
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 45
Designing High-Speed Adders in Power-Constrained Environments 45
Device-to-system level simulation framework for STT-DMTJ based cache memory 45
Evaluating the energy efficiency of stt-mrams based on perpendicular mtjs with double reference layers 45
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 44
An Embedded System for EEG Acquisition and Processing for Brain Computer Interface Applications 44
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates 44
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 42
An efficient wavelet image encoder for FPGA-based design 42
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor 42
Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain 42
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 42
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 41
Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers 41
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing 40
Design and Implementation of a 90nm low bit-rate image compression core 40
A tool to support harbor terminals design 40
Live demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI 40
Early Assessment of Tunnel-FET for Energy-Efficient Logic Circuits 39
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath 39
New Performance/Power/Area Efficient Reliable Full Adder Design 39
Cost-Effective Low-power Processor-In-Memory-based Reconfigurable datapath for Multimedia Applications 39
Impact of random process variations on different 65nm SRAM cell topologies 39
Digital and analog TFET circuits: Design and benchmark 39
A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks 39
Hardware implementation of a Test Lab for Smart Home environments 38
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design 38
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops 38
Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis 38
Low voltage Ripple Carry Adder with low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI 37
Ultra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits 37
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 37
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 37
SIMD 2-D Convolver for Fast FPGA-based Image and Video Processors 36
Totale 5.421
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Categoria #
all - tutte 44.689
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 44.689
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/201984 0 0 0 0 0 0 0 0 0 0 84 0
2019/2020936 88 86 3 90 75 241 67 99 17 19 100 51
2020/2021789 131 5 92 101 14 94 12 136 15 97 14 78
2021/20221.610 38 266 6 112 140 28 17 333 20 40 220 390
2022/20231.729 240 142 34 160 316 140 4 253 183 64 93 100
2023/2024897 146 61 111 39 78 123 57 99 108 72 3 0
Totale 6.402