IRIS
LANUZZA, MARCO
 Distribuzione geografica
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Continente #
NA - Nord America 12.903
AS - Asia 6.654
EU - Europa 3.674
SA - Sud America 1.884
AF - Africa 447
Continente sconosciuto - Info sul continente non disponibili 365
OC - Oceania 27
Totale 25.954
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Nazione #
US - Stati Uniti d'America 12.546
SG - Singapore 2.506
BR - Brasile 1.324
CN - Cina 1.189
VN - Vietnam 1.056
IT - Italia 895
UA - Ucraina 845
DE - Germania 685
HK - Hong Kong 484
BD - Bangladesh 358
FR - Francia 248
SE - Svezia 233
AR - Argentina 200
FI - Finlandia 177
IN - India 175
CA - Canada 171
SN - Senegal 169
TR - Turchia 140
KR - Corea 129
IQ - Iraq 114
RU - Federazione Russa 109
GB - Regno Unito 102
MX - Messico 95
EC - Ecuador 88
CO - Colombia 84
AT - Austria 79
ZA - Sudafrica 78
ID - Indonesia 68
NL - Olanda 64
VE - Venezuela 62
PK - Pakistan 60
MA - Marocco 56
CL - Cile 46
BE - Belgio 45
SA - Arabia Saudita 38
MY - Malesia 36
PY - Paraguay 36
TN - Tunisia 34
PL - Polonia 31
JO - Giordania 30
PH - Filippine 28
UZ - Uzbekistan 27
DZ - Algeria 26
AE - Emirati Arabi Uniti 25
ES - Italia 24
JP - Giappone 24
CZ - Repubblica Ceca 22
EG - Egitto 20
NP - Nepal 20
AU - Australia 19
PE - Perù 19
AZ - Azerbaigian 18
KE - Kenya 18
ET - Etiopia 16
IL - Israele 16
BO - Bolivia 13
OM - Oman 13
CR - Costa Rica 12
TW - Taiwan 12
CH - Svizzera 11
GT - Guatemala 11
IE - Irlanda 11
KZ - Kazakistan 11
UY - Uruguay 11
GR - Grecia 10
HN - Honduras 10
RO - Romania 10
JM - Giamaica 9
SV - El Salvador 9
BG - Bulgaria 8
DO - Repubblica Dominicana 8
KG - Kirghizistan 8
LB - Libano 8
NI - Nicaragua 8
PA - Panama 8
PS - Palestinian Territory 8
AL - Albania 7
HU - Ungheria 7
QA - Qatar 7
BY - Bielorussia 6
GE - Georgia 6
MD - Moldavia 6
TH - Thailandia 6
EU - Europa 5
GA - Gabon 5
HR - Croazia 5
KW - Kuwait 5
TT - Trinidad e Tobago 5
AO - Angola 4
BH - Bahrain 4
LV - Lettonia 4
MK - Macedonia 4
PT - Portogallo 4
RS - Serbia 4
AM - Armenia 3
BB - Barbados 3
CY - Cipro 3
DK - Danimarca 3
IR - Iran 3
LT - Lituania 3
Totale 25.528
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Città #
Dallas 6.379
Singapore 995
Chandler 605
Council Bluffs 528
San Jose 497
Jacksonville 448
Hong Kong 426
Ashburn 402
Ho Chi Minh City 347
Beijing 335
Boardman 329
San Mateo 303
Hanoi 260
Dearborn 250
New York 188
Dakar 169
Helsinki 164
Rende 161
Lauterbourg 153
Santa Clara 144
Milan 135
Lawrence 129
Shanghai 128
Roxbury 127
Hefei 123
Seoul 120
Bremen 114
São Paulo 104
Des Moines 87
Izmir 87
Ottawa 84
Los Angeles 83
Munich 78
Rome 73
Brooklyn 65
Vienna 60
Cambridge 59
Ann Arbor 57
Da Nang 56
Inglewood 55
Ogden 52
Bari 51
Amsterdam 49
Columbus 46
Chicago 45
Baghdad 44
Brussels 42
Wilmington 42
Haiphong 41
London 38
The Dalles 35
Biên Hòa 33
Falkenstein 33
Rio de Janeiro 33
San Francisco 33
Buffalo 32
Johannesburg 31
Guayaquil 30
Mexico City 30
West Jordan 30
Toronto 28
Amman 27
Quito 27
Tianjin 27
Brasília 26
Tashkent 26
Dhaka 25
Mumbai 25
Belo Horizonte 24
Bogotá 24
Cosenza 24
Frankfurt am Main 24
Curitiba 23
Guangzhou 23
Hải Dương 23
Warsaw 23
Phoenix 22
Naples 21
Cape Town 20
Guarulhos 20
Houston 20
Turin 20
Can Tho 19
Bologna 18
Catania 18
Lahore 17
Medellín 17
Santiago 17
Baku 16
Caracas 16
Fortaleza 16
Nairobi 16
Campinas 15
Casablanca 15
Istanbul 15
Quảng Ngãi 15
St Petersburg 15
Tokyo 15
Tunis 15
Catanzaro 14
Totale 16.488
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Nome #
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 1.512
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 1.465
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 1.457
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 1.457
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 1.395
A high-performance fully reconfigurable FPGA-based 2D convolution processor 214
An Ultralow-Voltage Energy-Efficient Level Shifter 197
A novel ICA-based hardware system for reconfigurable and portable BCI 191
Design of a 3T current reference for low-voltage, low-power operation 190
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC 189
A comparative study of MWT architectures by means of numerical simulations 167
A new reconfigurable coarse-grain architecture for multimedia applications 166
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 166
A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks 166
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI 160
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits 160
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 158
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 158
A 180 nm Low-Cost Operational Amplifier for IoT Applications 158
A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance 156
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 156
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 150
A portable class of 3-transistor current references with low-power sub-0.5 V operation 147
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 144
Opto-electrical modelling and optimization study of a novel IBC c-Si solar cell 144
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 143
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 142
A new low-power high-speed single-clock-cycle binary comparator 141
Spin-orbit torque based physical unclonable function 141
PUF-Based Authentication-Oriented Architecture for Identification Tags 140
Designing Dynamic Carry Skip Adders: Analysis and Comparison 140
A variation-aware simulation framework for hybrid CMOS/spintronic circuits 139
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 137
An efficient wavelet image encoder for FPGA-based design 137
Low-power split-path data-driven dynamic logic 136
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 136
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design 135
Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology 134
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions 133
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 132
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification 131
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmentic circuits 131
Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations 131
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 131
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation 130
Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework 130
Live demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI 128
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework 126
Variable precision arithmetic circuits for FPGA-based multimedia processors 125
Low energy/delay overhead level shifter for wide-range voltage conversion 125
Comparative analysis of yield optimized pulsed flip-flops 125
Evaluation of Dual Mode Logic in 28nm FD-SOI technology 125
Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations 124
EDAM: Edit Distance tolerant Approximate Matching content addressable memory 124
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines 124
Low-Power Level Shifter for Multi-Supply Voltage Designs 124
Dynamic gate-level body biasing for subthreshold digital design 124
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs 124
Device-to-system level simulation framework for STT-DMTJ based cache memory 124
Design of a sub-1-V nanopower CMOS current reference 124
A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters 123
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 121
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 121
Skyrmion based microwave detectors and harvesting 121
Hardware implementation of a Test Lab for Smart Home environments 121
Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers 121
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW 121
Robust dual mode pass logic (DMPL) for energy efficiency and high performance 121
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 120
Low bit rate image compression core for onboard space applications 119
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 119
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 118
Improving Reliability of STT-MRAM-Based Smart Material Implication 116
A tool to support harbor terminals design 116
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits 116
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 115
Design and evaluation of high-speed energy-aware carry skip adders 115
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits 115
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits 114
Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells 112
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 112
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 111
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 109
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 109
Cost-Effective Low-power Processor-In-Memory-based Reconfigurable datapath for Multimedia Applications 109
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 108
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 108
Exploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology 108
AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing 107
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops 107
Double-precision Dual Mode Logic carry-save multiplier 107
Evaluating the energy efficiency of stt-mrams based on perpendicular mtjs with double reference layers 107
Improving speed and power characteristics of pulse-triggered flip-flops 106
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 106
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 105
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor 104
Designing High-Speed Adders in Power-Constrained Environments 104
A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance 103
Design and Implementation of a 90nm low bit-rate image compression core 103
An energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops 103
Totale 19.720
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Categoria #
all - tutte 117.599
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 117.599
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20221.572 0 266 6 112 140 28 17 333 20 40 220 390
2022/20231.729 240 142 34 160 316 140 4 253 183 64 93 100
2023/20241.157 146 61 111 39 78 123 57 99 108 72 59 204
2024/20252.965 55 364 79 164 239 201 219 178 427 106 234 699
2025/202615.455 1.015 1.521 5.580 1.077 1.570 750 921 447 599 757 585 633
2026/2027872 598 274 0 0 0 0 0 0 0 0 0 0
Totale 25.954