IRIS
LANUZZA, MARCO
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 14.063
AS - Asia 6.672
EU - Europa 4.007
SA - Sud America 1.891
AF - Africa 452
Continente sconosciuto - Info sul continente non disponibili 373
OC - Oceania 27
Totale 27.485
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 13.608
SG - Singapore 2.508
BR - Brasile 1.327
CN - Cina 1.192
IT - Italia 1.192
VN - Vietnam 1.057
UA - Ucraina 847
DE - Germania 685
HK - Hong Kong 484
BD - Bangladesh 361
FR - Francia 248
SE - Svezia 233
CA - Canada 205
AR - Argentina 201
IN - India 178
FI - Finlandia 177
SN - Senegal 169
TR - Turchia 141
KR - Corea 129
RU - Federazione Russa 120
GB - Regno Unito 118
IQ - Iraq 114
MX - Messico 95
EC - Ecuador 89
CO - Colombia 85
AT - Austria 79
ZA - Sudafrica 78
ID - Indonesia 69
NL - Olanda 65
VE - Venezuela 63
PK - Pakistan 60
MA - Marocco 56
BE - Belgio 46
CL - Cile 46
SA - Arabia Saudita 38
MY - Malesia 37
PY - Paraguay 36
TN - Tunisia 34
PL - Polonia 31
JO - Giordania 30
PH - Filippine 28
UZ - Uzbekistan 27
DZ - Algeria 26
AE - Emirati Arabi Uniti 25
ES - Italia 25
JP - Giappone 25
CZ - Repubblica Ceca 22
EG - Egitto 20
NP - Nepal 20
SV - El Salvador 20
AU - Australia 19
CR - Costa Rica 19
HN - Honduras 19
PE - Perù 19
AZ - Azerbaigian 18
KE - Kenya 18
GT - Guatemala 17
IL - Israele 17
ET - Etiopia 16
PR - Porto Rico 14
BO - Bolivia 13
NI - Nicaragua 13
OM - Oman 13
TW - Taiwan 13
RO - Romania 12
CH - Svizzera 11
IE - Irlanda 11
KZ - Kazakistan 11
UY - Uruguay 11
GR - Grecia 10
JM - Giamaica 10
PA - Panama 9
TT - Trinidad e Tobago 9
BG - Bulgaria 8
CW - ???statistics.table.value.countryCode.CW??? 8
DO - Repubblica Dominicana 8
KG - Kirghizistan 8
LB - Libano 8
PS - Palestinian Territory 8
AL - Albania 7
HU - Ungheria 7
QA - Qatar 7
BY - Bielorussia 6
GE - Georgia 6
GP - Guadalupe 6
MD - Moldavia 6
SC - Seychelles 6
TH - Thailandia 6
EU - Europa 5
GA - Gabon 5
HR - Croazia 5
KW - Kuwait 5
AO - Angola 4
BB - Barbados 4
BH - Bahrain 4
LV - Lettonia 4
MK - Macedonia 4
PT - Portogallo 4
RS - Serbia 4
AM - Armenia 3
Totale 27.047
Salva come PNG Salva come JPEG
Città #
Dallas 6.384
Singapore 995
Council Bluffs 739
San Jose 665
Chandler 605
Ashburn 604
Jacksonville 448
Hong Kong 426
Ho Chi Minh City 347
Beijing 337
Boardman 329
San Mateo 303
Hanoi 260
Dearborn 250
Milan 236
New York 211
Dakar 169
Helsinki 164
Rende 161
Santa Clara 155
Lauterbourg 153
Lawrence 129
Shanghai 128
Roxbury 127
Hefei 123
Seoul 120
Bremen 114
São Paulo 105
Chicago 96
Rome 88
Des Moines 87
Izmir 87
Los Angeles 87
Ottawa 85
Munich 78
Brooklyn 69
Vienna 60
Cambridge 59
Ann Arbor 58
Da Nang 56
Inglewood 55
Bari 53
Ogden 52
Amsterdam 50
Columbus 46
Baghdad 44
Wilmington 43
Brussels 42
Haiphong 41
London 41
Phoenix 38
Buffalo 37
San Francisco 35
The Dalles 35
Biên Hòa 33
Falkenstein 33
Miano 33
Rio de Janeiro 33
Toronto 32
Guayaquil 31
Johannesburg 31
Mexico City 30
Naples 30
West Jordan 30
Amman 27
Brasília 27
Quito 27
Tianjin 27
Mumbai 26
Tashkent 26
Atlanta 25
Dhaka 25
Belo Horizonte 24
Bogotá 24
Bologna 24
Cosenza 24
Frankfurt am Main 24
Curitiba 23
Guangzhou 23
Hải Dương 23
Warsaw 23
Houston 22
Turin 22
Montreal 21
Cape Town 20
Guarulhos 20
Princeton 20
Can Tho 19
Catania 19
Charlotte 18
San Salvador 18
Lahore 17
Medellín 17
Palermo 17
Santiago 17
Baku 16
Caracas 16
Fortaleza 16
Nairobi 16
Tokyo 16
Totale 17.394
Salva come PNG Salva come JPEG
Nome #
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 1.529
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 1.486
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 1.473
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 1.473
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 1.409
A high-performance fully reconfigurable FPGA-based 2D convolution processor 225
A novel ICA-based hardware system for reconfigurable and portable BCI 209
An Ultralow-Voltage Energy-Efficient Level Shifter 204
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC 203
Design of a 3T current reference for low-voltage, low-power operation 198
A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks 180
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 178
A comparative study of MWT architectures by means of numerical simulations 177
A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance 173
A new reconfigurable coarse-grain architecture for multimedia applications 172
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 170
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 168
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits 168
A 180 nm Low-Cost Operational Amplifier for IoT Applications 166
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI 165
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 164
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 161
A portable class of 3-transistor current references with low-power sub-0.5 V operation 158
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 155
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 153
A variation-aware simulation framework for hybrid CMOS/spintronic circuits 152
PUF-Based Authentication-Oriented Architecture for Identification Tags 150
Opto-electrical modelling and optimization study of a novel IBC c-Si solar cell 150
A new low-power high-speed single-clock-cycle binary comparator 149
Designing Dynamic Carry Skip Adders: Analysis and Comparison 148
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 147
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 147
Spin-orbit torque based physical unclonable function 147
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 144
An efficient wavelet image encoder for FPGA-based design 144
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation 143
Low-power split-path data-driven dynamic logic 143
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits 143
Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology 143
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions 143
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 142
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification 141
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design 141
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 141
Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework 139
Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations 138
Low energy/delay overhead level shifter for wide-range voltage conversion 136
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmentic circuits 136
EDAM: Edit Distance tolerant Approximate Matching content addressable memory 135
Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations 134
Comparative analysis of yield optimized pulsed flip-flops 134
Variable precision arithmetic circuits for FPGA-based multimedia processors 133
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework 133
Design of a sub-1-V nanopower CMOS current reference 133
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines 132
Low-Power Level Shifter for Multi-Supply Voltage Designs 132
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops 132
Dynamic gate-level body biasing for subthreshold digital design 132
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs 132
A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters 132
Live demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI 132
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 131
Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers 131
Evaluation of Dual Mode Logic in 28nm FD-SOI technology 131
Device-to-system level simulation framework for STT-DMTJ based cache memory 129
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 128
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW 128
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 128
Skyrmion based microwave detectors and harvesting 127
Hardware implementation of a Test Lab for Smart Home environments 127
Low bit rate image compression core for onboard space applications 127
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 127
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 126
Robust dual mode pass logic (DMPL) for energy efficiency and high performance 126
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 125
Design and evaluation of high-speed energy-aware carry skip adders 124
Improving Reliability of STT-MRAM-Based Smart Material Implication 123
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 123
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 123
A tool to support harbor terminals design 122
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits 122
Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells 121
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits 120
A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance 119
AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing 116
Cost-Effective Low-power Processor-In-Memory-based Reconfigurable datapath for Multimedia Applications 116
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 116
Exploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology 115
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 114
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 114
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates 114
Evaluating the energy efficiency of stt-mrams based on perpendicular mtjs with double reference layers 114
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 113
Double-precision Dual Mode Logic carry-save multiplier 113
Designing High-Speed Adders in Power-Constrained Environments 112
Improving speed and power characteristics of pulse-triggered flip-flops 112
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 112
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 111
Design and Implementation of a 90nm low bit-rate image compression core 109
An energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops 109
Totale 20.648
Salva come PNG Salva come JPEG
Categoria #
all - tutte 123.433
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 123.433
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20221.300 0 0 0 112 140 28 17 333 20 40 220 390
2022/20231.729 240 142 34 160 316 140 4 253 183 64 93 100
2023/20241.157 146 61 111 39 78 123 57 99 108 72 59 204
2024/20252.965 55 364 79 164 239 201 219 178 427 106 234 699
2025/202615.455 1.015 1.521 5.580 1.077 1.570 750 921 447 599 757 585 633
2026/20272.403 598 310 436 1.059 0 0 0 0 0 0 0 0
Totale 27.485