IRIS
LANUZZA, Marco
 Distribuzione geografica
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Continente #
NA - Nord America 3.784
EU - Europa 2.259
AS - Asia 986
AF - Africa 167
OC - Oceania 12
SA - Sud America 10
Continente sconosciuto - Info sul continente non disponibili 5
Totale 7.223
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Nazione #
US - Stati Uniti d'America 3.688
UA - Ucraina 806
DE - Germania 550
SG - Singapore 443
IT - Italia 371
CN - Cina 325
SE - Svezia 227
SN - Senegal 163
CA - Canada 95
TR - Turchia 94
FI - Finlandia 81
AT - Austria 54
HK - Hong Kong 52
GB - Regno Unito 35
BE - Belgio 33
FR - Francia 25
NL - Olanda 22
CZ - Repubblica Ceca 17
IN - India 16
IQ - Iraq 13
KR - Corea 12
AU - Australia 11
BR - Brasile 9
RU - Federazione Russa 9
IL - Israele 7
JP - Giappone 6
EU - Europa 5
IE - Irlanda 5
PL - Polonia 5
TW - Taiwan 4
GR - Grecia 3
HR - Croazia 2
ID - Indonesia 2
MY - Malesia 2
PK - Pakistan 2
PT - Portogallo 2
RO - Romania 2
ZA - Sudafrica 2
AE - Emirati Arabi Uniti 1
AM - Armenia 1
CH - Svizzera 1
EG - Egitto 1
ES - Italia 1
GE - Georgia 1
HU - Ungheria 1
KW - Kuwait 1
LT - Lituania 1
LU - Lussemburgo 1
LV - Lettonia 1
MD - Moldavia 1
MK - Macedonia 1
MO - Macao, regione amministrativa speciale della Cina 1
MX - Messico 1
NO - Norvegia 1
NZ - Nuova Zelanda 1
PE - Perù 1
PH - Filippine 1
SK - Slovacchia (Repubblica Slovacca) 1
SL - Sierra Leone 1
TH - Thailandia 1
VN - Vietnam 1
Totale 7.223
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Città #
Chandler 605
Jacksonville 443
Singapore 337
Boardman 329
San Mateo 303
Dearborn 250
Dakar 163
Rende 133
Lawrence 129
Roxbury 127
Shanghai 120
Bremen 114
Des Moines 87
Izmir 83
New York 83
Ottawa 80
Helsinki 76
Ashburn 71
Cambridge 59
Ann Arbor 57
Inglewood 55
Ogden 52
Vienna 47
Brooklyn 45
Wilmington 41
Beijing 40
Bari 37
Chicago 31
Brussels 30
Milan 30
West Jordan 30
Munich 28
Amsterdam 20
London 19
Cosenza 16
Los Angeles 16
Guangzhou 14
San Francisco 14
Grafing 13
Redwood City 12
Santa Clara 12
Brno 11
Central 11
Falls Church 11
Houston 11
Rome 11
Toronto 11
Cedar Knolls 10
Bologna 8
Hong Kong 8
Nanjing 8
Norwalk 8
Turin 8
Frankfurt am Main 7
Ningbo 7
Catanzaro 6
Palermo 6
Paris 6
Seattle 6
Seoul 6
Vibo Valentia 6
Dublin 5
Gangnam-gu 5
Istanbul 5
Kilburn 5
Lappeenranta 5
Spadola 5
Sydney 5
Florence 4
Mascalucia 4
Melbourne 4
Monmouth Junction 4
Washington 4
Wuhan 4
Changsha 3
Giv‘atayim 3
Gunzenhausen 3
Haikou 3
Heusden-Zolder 3
Jiaxing 3
Markham 3
Osaka 3
Princeton 3
Redmond 3
Serra 3
Tokyo 3
Warsaw 3
Woodbridge 3
Xi'an 3
Yiwu 3
Arcueil 2
Athens 2
Augusta 2
Berlin 2
Bomporto 2
Brunoy 2
Buffalo 2
Canberra 2
Carrara 2
Catania 2
Totale 4.544
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Nome #
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 145
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 142
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 120
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 119
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC 109
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 95
An Ultralow-Voltage Energy-Efficient Level Shifter 95
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 84
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 84
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 82
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 82
A high-performance fully reconfigurable FPGA-based 2D convolution processor 80
Designing Dynamic Carry Skip Adders: Analysis and Comparison 78
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 77
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 77
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs 73
Low-power split-path data-driven dynamic logic 72
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits 72
A comparative study of MWT architectures by means of numerical simulations 72
Comparative analysis of yield optimized pulsed flip-flops 71
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits 71
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 70
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions 69
Design of a sub-1-V nanopower CMOS current reference 68
A portable class of 3-transistor current references with low-power sub-0.5 V operation 67
A 180 nm Low-Cost Operational Amplifier for IoT Applications 67
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 66
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits 66
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 66
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmentic circuits 65
A novel ICA-based hardware system for reconfigurable and portable BCI 65
A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters 65
Low energy/delay overhead level shifter for wide-range voltage conversion 64
Low-Power Level Shifter for Multi-Supply Voltage Designs 63
Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations 63
Variable precision arithmetic circuits for FPGA-based multimedia processors 61
Design of a 3T current reference for low-voltage, low-power operation 61
Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework 61
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 61
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI 60
Skyrmion based microwave detectors and harvesting 59
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 59
Design and evaluation of high-speed energy-aware carry skip adders 59
Opto-electrical modelling and optimization study of a novel IBC c-Si solar cell 59
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 59
Evaluation of Dual Mode Logic in 28nm FD-SOI technology 59
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 58
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines 58
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits 58
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework 57
Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells 56
Impact of the Emitter Contact Pattern in c-Si BC-BJ Solar Cells by Numerical Simulations 56
A variation-aware simulation framework for hybrid CMOS/spintronic circuits 55
Low bit rate image compression core for onboard space applications 55
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 55
Spin-orbit torque based physical unclonable function 55
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 54
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 54
A new low-power high-speed single-clock-cycle binary comparator 54
A new reconfigurable coarse-grain architecture for multimedia applications 54
Optimization of Rear Point Contact Geometry by Means of 3-D Numerical Simulation 54
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing 53
Double-precision Dual Mode Logic carry-save multiplier 53
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 52
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 52
Designing High-Speed Adders in Power-Constrained Environments 52
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 52
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs 52
Device-to-system level simulation framework for STT-DMTJ based cache memory 52
An Embedded System for EEG Acquisition and Processing for Brain Computer Interface Applications 51
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates 51
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 51
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 49
Evaluating the energy efficiency of stt-mrams based on perpendicular mtjs with double reference layers 49
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 48
A tool to support harbor terminals design 48
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 48
Impact of random process variations on different 65nm SRAM cell topologies 47
Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain 47
Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers 47
Hardware implementation of a Test Lab for Smart Home environments 46
An efficient wavelet image encoder for FPGA-based design 46
Design and Implementation of a 90nm low bit-rate image compression core 46
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design 46
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor 46
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops 46
Live demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI 46
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 46
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing 45
Early Assessment of Tunnel-FET for Energy-Efficient Logic Circuits 45
Digital and analog TFET circuits: Design and benchmark 45
A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks 45
Cost-Effective Low-power Processor-In-Memory-based Reconfigurable datapath for Multimedia Applications 44
Low voltage Ripple Carry Adder with low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI 43
New Performance/Power/Area Efficient Reliable Full Adder Design 43
Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology 43
Dynamic gate-level body biasing for subthreshold digital design 43
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 43
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW 43
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 42
Totale 6.161
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Categoria #
all - tutte 59.980
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 59.980
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020669 0 0 0 0 75 241 67 99 17 19 100 51
2020/2021789 131 5 92 101 14 94 12 136 15 97 14 78
2021/20221.610 38 266 6 112 140 28 17 333 20 40 220 390
2022/20231.729 240 142 34 160 316 140 4 253 183 64 93 100
2023/20241.157 146 61 111 39 78 123 57 99 108 72 59 204
2024/2025878 55 364 79 164 216 0 0 0 0 0 0 0
Totale 7.540