IRIS
LANUZZA, MARCO
 Distribuzione geografica
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Continente #
NA - Nord America 11.672
AS - Asia 6.147
EU - Europa 3.318
SA - Sud America 1.853
AF - Africa 445
OC - Oceania 25
Continente sconosciuto - Info sul continente non disponibili 8
Totale 23.468
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Nazione #
US - Stati Uniti d'America 11.381
SG - Singapore 2.449
BR - Brasile 1.314
VN - Vietnam 1.044
CN - Cina 1.041
UA - Ucraina 842
DE - Germania 684
IT - Italia 573
HK - Hong Kong 473
FR - Francia 245
SE - Svezia 233
AR - Argentina 199
FI - Finlandia 177
SN - Senegal 169
IN - India 158
TR - Turchia 140
CA - Canada 139
KR - Corea 129
BD - Bangladesh 126
IQ - Iraq 114
RU - Federazione Russa 108
MX - Messico 90
EC - Ecuador 87
GB - Regno Unito 85
AT - Austria 79
ZA - Sudafrica 78
CO - Colombia 74
ID - Indonesia 64
NL - Olanda 63
PK - Pakistan 60
VE - Venezuela 59
MA - Marocco 56
BE - Belgio 45
CL - Cile 43
PY - Paraguay 36
SA - Arabia Saudita 36
TN - Tunisia 33
JO - Giordania 30
PL - Polonia 30
MY - Malesia 28
UZ - Uzbekistan 27
DZ - Algeria 26
PH - Filippine 25
JP - Giappone 23
CZ - Repubblica Ceca 21
ES - Italia 21
EG - Egitto 20
AE - Emirati Arabi Uniti 19
PE - Perù 19
AU - Australia 18
AZ - Azerbaigian 18
KE - Kenya 18
NP - Nepal 18
ET - Etiopia 16
IL - Israele 16
OM - Oman 13
BO - Bolivia 12
CH - Svizzera 11
IE - Irlanda 11
KZ - Kazakistan 11
TW - Taiwan 11
GR - Grecia 10
RO - Romania 10
UY - Uruguay 10
BG - Bulgaria 8
CR - Costa Rica 8
DO - Repubblica Dominicana 8
GT - Guatemala 8
KG - Kirghizistan 8
LB - Libano 8
PA - Panama 8
PS - Palestinian Territory 8
AL - Albania 7
BY - Bielorussia 6
GE - Georgia 6
HN - Honduras 6
HU - Ungheria 6
QA - Qatar 6
EU - Europa 5
GA - Gabon 5
HR - Croazia 5
JM - Giamaica 5
KW - Kuwait 5
MD - Moldavia 5
NI - Nicaragua 5
TH - Thailandia 5
TT - Trinidad e Tobago 5
AO - Angola 4
BH - Bahrain 4
LV - Lettonia 4
MK - Macedonia 4
RS - Serbia 4
SV - El Salvador 4
AM - Armenia 3
BB - Barbados 3
CY - Cipro 3
DK - Danimarca 3
IR - Iran 3
LT - Lituania 3
LY - Libia 3
Totale 23.409
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Città #
Dallas 6.366
Singapore 980
Chandler 605
San Jose 450
Jacksonville 445
Hong Kong 418
Ho Chi Minh City 343
Boardman 329
Ashburn 308
San Mateo 303
Beijing 300
Hanoi 257
Dearborn 250
Dakar 169
Helsinki 164
Rende 154
Lauterbourg 153
Lawrence 129
Roxbury 127
Shanghai 126
Hefei 122
Seoul 120
Bremen 114
New York 112
São Paulo 103
Des Moines 87
Izmir 87
Ottawa 84
Munich 78
Brooklyn 62
Vienna 60
Cambridge 59
Ann Arbor 57
Da Nang 55
Inglewood 55
Milan 55
Los Angeles 52
Ogden 52
Council Bluffs 50
Amsterdam 49
Santa Clara 45
Baghdad 44
Brussels 42
Haiphong 41
Wilmington 41
Chicago 40
Bari 39
Columbus 35
The Dalles 35
Biên Hòa 33
Falkenstein 33
Rio de Janeiro 33
San Francisco 32
Johannesburg 31
Guayaquil 30
West Jordan 30
Mexico City 29
Rome 29
Amman 27
Tianjin 27
London 26
Quito 26
Tashkent 26
Brasília 25
Belo Horizonte 24
Cosenza 24
Frankfurt am Main 24
Curitiba 23
Guangzhou 23
Hải Dương 23
Warsaw 23
Dhaka 22
Cape Town 20
Bogotá 19
Can Tho 19
Guarulhos 19
Toronto 19
Lahore 17
Medellín 17
Baku 16
Caracas 16
Nairobi 16
Campinas 15
Casablanca 15
Fortaleza 15
Istanbul 15
Quảng Ngãi 15
Santiago 15
St Petersburg 15
Tokyo 15
Catanzaro 14
Lima 14
Ninh Bình 14
Porto Alegre 14
Thái Nguyên 14
Tunis 14
Addis Ababa 13
Asunción 13
Buenos Aires 13
Catania 13
Totale 15.308
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Nome #
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 1.481
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 1.440
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 1.433
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 1.429
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 1.379
A high-performance fully reconfigurable FPGA-based 2D convolution processor 183
An Ultralow-Voltage Energy-Efficient Level Shifter 181
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC 173
A comparative study of MWT architectures by means of numerical simulations 160
A novel ICA-based hardware system for reconfigurable and portable BCI 156
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 155
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 152
A 180 nm Low-Cost Operational Amplifier for IoT Applications 152
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits 150
A new reconfigurable coarse-grain architecture for multimedia applications 149
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 149
A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance 144
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 144
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI 141
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 138
A new low-power high-speed single-clock-cycle binary comparator 137
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 137
A portable class of 3-transistor current references with low-power sub-0.5 V operation 136
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 135
A variation-aware simulation framework for hybrid CMOS/spintronic circuits 135
Designing Dynamic Carry Skip Adders: Analysis and Comparison 134
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 133
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 133
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 131
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions 131
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmentic circuits 130
Opto-electrical modelling and optimization study of a novel IBC c-Si solar cell 127
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 126
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 125
PUF-Based Authentication-Oriented Architecture for Identification Tags 124
Spin-orbit torque based physical unclonable function 122
A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks 122
An efficient wavelet image encoder for FPGA-based design 121
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs 120
Design of a sub-1-V nanopower CMOS current reference 120
A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters 119
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 119
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 117
Low energy/delay overhead level shifter for wide-range voltage conversion 117
Device-to-system level simulation framework for STT-DMTJ based cache memory 117
Evaluation of Dual Mode Logic in 28nm FD-SOI technology 117
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 116
Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework 116
Dynamic gate-level body biasing for subthreshold digital design 115
Comparative analysis of yield optimized pulsed flip-flops 115
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 115
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation 114
Variable precision arithmetic circuits for FPGA-based multimedia processors 114
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines 114
Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations 113
Skyrmion based microwave detectors and harvesting 113
Low-Power Level Shifter for Multi-Supply Voltage Designs 113
Design of a 3T current reference for low-voltage, low-power operation 113
Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology 112
Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations 112
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 112
Low-power split-path data-driven dynamic logic 110
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW 110
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification 108
Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells 108
Design and evaluation of high-speed energy-aware carry skip adders 108
A tool to support harbor terminals design 108
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits 107
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework 107
Live demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI 107
Hardware implementation of a Test Lab for Smart Home environments 106
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design 106
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 106
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 105
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 104
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 104
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits 104
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits 104
Low bit rate image compression core for onboard space applications 104
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 102
Double-precision Dual Mode Logic carry-save multiplier 102
EDAM: Edit Distance tolerant Approximate Matching content addressable memory 101
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 101
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 100
An energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops 100
AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing 99
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 99
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 98
Cost-Effective Low-power Processor-In-Memory-based Reconfigurable datapath for Multimedia Applications 97
Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers 97
Exploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology 97
Improving speed and power characteristics of pulse-triggered flip-flops 96
Evaluating the energy efficiency of stt-mrams based on perpendicular mtjs with double reference layers 96
New Performance/Power/Area Efficient Reliable Full Adder Design 94
Designing High-Speed Adders in Power-Constrained Environments 94
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates 92
Digital and analog TFET circuits: Design and benchmark 92
Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis 92
Early Assessment of Tunnel-FET for Energy-Efficient Logic Circuits 91
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops 91
Totale 18.428
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Categoria #
all - tutte 107.825
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 107.825
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021189 0 0 0 0 0 0 0 0 0 97 14 78
2021/20221.610 38 266 6 112 140 28 17 333 20 40 220 390
2022/20231.729 240 142 34 160 316 140 4 253 183 64 93 100
2023/20241.157 146 61 111 39 78 123 57 99 108 72 59 204
2024/20252.965 55 364 79 164 239 201 219 178 427 106 234 699
2025/202614.193 1.015 1.521 5.580 1.077 1.570 750 921 447 599 713 0 0
Totale 23.820